The push for high speed computing has led to the development of high speed, time-constrained, asynchronous links such as IBM's self-timed interfaces (STIs). In fact, the STI has been implemented in IBM's largest servers for several generations, providing successively improved input-output (I/O) subsystem bandwidth capacities. Time-constrained, asynchronous links are asynchronous data interfaces that transmit data over parallel bit lines via independent clock signals that are substantially synchronized at times. In particular, time-constrained, asynchronous interfaces, sometimes referred to as elastic or semi-static interfaces, may guarantee synchronous behavior over a specified time interval to facilitate data transfers.
For purposes of the data transfers, the synchronous nature of the elastic interfaces is limited to a time interval following the initial transmission and receipt of a test pattern of data. The test pattern data is examined to determine the timing relationship or skew pattern between bits received via different bit lines of the bus. Thereafter, for the extent of the time interval, data crossing the interface may be presumed to follow the same skew pattern. Receive logic identifies the skew pattern based upon the test pattern data and determines the timing required to synchronously capture subsequent data sent across the same interface.
Elastic interfaces make use of the knowledge that the change in phase between independently driven clocks will occur over time and that the rate of change is fairly constant. In particular, clocks for the elastic interface will stay reasonably in phase for the time interval and, thus, for that time interval, the clocks can be viewed as being effectively synchronous for data transfers. However, after the expiration of the time interval, the elastic interface is asynchronous again.
When testing circuit performance with regards to communication across an elastic interface, circuit designers must verify that the circuit can transfer data during the specified time intervals. Otherwise, the circuit will not function properly.
To verify the circuit's performance, designers utilize circuit simulators to simulate the circuit's performance prior to the investment of large amounts of capital to build the circuit. Ideally, circuit simulations accurately simulate every potentially problematic aspect of the circuit operation. The problem with current circuit simulators from the perspective of the elastic interface is that skew/jitter logic is employed to model asynchronous behavior. The skew/jitter logic is non-deterministic—i.e. the phase shift employed for a signal is always non-static. So skew/jitter logic cannot be used for elastic interfaces or other semi-static interfaces that require that the skew/jitter imposed remains static for a period of time.
The current solution for this problem is to employ a static skew pattern. This avoids the deficiency in circuit simulation of the elastic interface. The static skew pattern simulates one skew pattern of the elastic interface, however, this solution fails to simulate asynchronous behavior of the elastic interface at the expiration of the synchronous time interval, which is a potentially problematic aspect of the circuit operation.